Semiconductor package, method of manufacturing the same, and semiconductor device

ABSTRACT

A wiring layer for serving as a first electrode layer of a capacitor portion patterned in a predetermined shape on an insulative base member is formed. A resin layer for serving as a dielectric layer of the capacitor portion is formed on a surface of the wiring layer using an electrophoretic process. Another wiring layer for serving as a second electrode layer of the capacitor portion patterned in a predetermined shape by patterning on the insulative base member inclusive of the resin layer is formed.

BACKGROUND OF THE INVENTION

[0001] (a) Field of the Invention

[0002] The present invention relates to technologies for manufacturingmultilayer wiring boards used as packages for mounting semiconductorelements (hereinafter referred to as “semiconductor packages”). Morespecifically, the present invention relates to a semiconductor packagecontaining a capacitor portion using a conductive resin layer formed ona wiring layer, a method of manufacturing the same and a semiconductordevice.

[0003] (b) Description of the Related Art

[0004] In order to meet demands for higher density, semiconductorpackages in recent years include wiring patterns which are disposedclosely to one another. Accordingly, such semiconductor packages wouldincur problems such as occurrence of crosstalk noises between aplurality of wiring, or fluctuation of electric potential of powersource line and the like. In particular, a package for mounting asemiconductor element for high-frequency use, in which high-speedswitching operations are required, tends to incur crosstalk noises alongwith an increase in frequency or incur switching noises because aswitching element therein is turned on and off in a high speed. As aresult, electric potential of a power source line and the like tends tovary easily.

[0005] Therefore, as a remedy for the foregoing problems, “decoupling”of a signal line or a power source line has been heretofore put intopractice. Such decoupling is carried out by adding capacitor elementssuch as chip capacitors to a package mounting a semiconductor elementthereon.

[0006] However, in this case, design freedom of wiring patterns may berestricted by provision of the chip capacitors, or an increase ininductance may be incurred due to elongated wiring patterns forconnecting the chip capacitors and power/ground terminals of thesemiconductor element. As the decoupling effect of the chip capacitor isimpaired where the inductance is large, it is preferred to set theinductance as small as possible. In other words, it is desirable todispose the capacitor elements such as chip capacitors as close to thesemiconductor element as possible.

[0007] There is also a risk that the package becomes larger and heavieras a whole because the capacitor elements such as chip capacitors areadded to the package, which goes against the tide of downsizing andweight saving of semiconductor packages in recent years.

[0008] Therefore, instead of adding the capacitor elements such as chipcapacitors to the package, it is conceivable to allow the package tocontain equivalent capacitor elements (capacitor portions) in order todeal with the above-mentioned inconveniences.

[0009] Conventionally, technologies for building the capacitor portioninto the package have been limited to a few methods, such as a method oflaminating a sheet member containing inorganic filler for improvingdielectric constant between wiring layers, as a dielectric layer of thecapacitor portion.

[0010] As described above, in the conventional semiconductor package,the sheet member made of a high-dielectric material is laminated betweenthe wiring layers as the dielectric layer of the capacitor portions inthe case of allowing the package to contain the capacitor elements (thecapacitor portions) for exerting the decoupling effect. In this context,it is necessary to form an insulating layer between the wiring layersthicker than the dielectric layer concerned. Accordingly, there arisesan inconvenience in that the thickness of the interlayer insulating filmcannot be sufficiently made thin.

[0011] Such an inconvenience inhibits formation of a low-profilesemiconductor package and resultantly goes against the tide of recentdemands for providing a high-density equipped semiconductor device whilereducing an entire thickness of the package. In addition, costs for aninterlayer insulating film rise as a film thickness thereof increases.As a result, there is also a problem of an increase in manufacturingcosts of the package.

SUMMARY OF THE INVENTION

[0012] An object of the present invention is to provide a semiconductorpackage capable of containing a capacitor portion for exerting adecoupling effect without inhibiting formation of a low-profile packageor increasing manufacturing cost, and also to provide a manufacturingmethod thereof and a semiconductor device.

[0013] To attain the above object, according to one aspect of thepresent invention, there is provided a method of manufacturing asemiconductor package containing a capacitor portion. Here, the methodincludes the steps of forming a first wiring layer on an insulative basemember, the first wiring layer being patterned in a predetermined shapefor serving as a first electrode layer of the capacitor portion, forminga resin layer on a surface of the first wiring layer for serving as adielectric layer of the capacitor layer by an electrophoretic depositionprocess, and forming a second wiring layer on the insulative base memberinclusive of the resin layer, the second wiring layer being patterned ina predetermined shape for serving as a second electrode layer of thecapacitor portion.

[0014] According to the method of manufacturing a semiconductor packageof the present invention, it is possible to constitute the capacitorportion by using the resin layer formed on the first wiring layer on theinsulative base member by the electrophoretic deposition process as thedielectric layer and by using the first wiring layer and the secondwiring layer formed on the insulative base member inclusive of the resinlayer severally as electrode layers.

[0015] In this way, a desired decoupling effect (suppression ofoccurrence of crosstalk noises between a plurality of wiring,suppression of variation in electric potential of a power source line,and the like) can be realized. Moreover, some of the membersconstituting the package (namely, the first and the second wiring layersand the resin layer) are also used as the respective electrode layersand as the dielectric layer of the capacitor portion. Accordingly, it isunnecessary to build a sheet member into the package for capacitorelements as encountered in the prior art. Such an advantage contributesto a formation of a low-profile semiconductor package as well as to areduction in manufacturing costs.

[0016] Moreover, according to another aspect of the present invention,there is provided a semiconductor package manufactured in accordancewith the above-described method of manufacturing a semiconductorpackage.

[0017] Furthermore, according to still another aspect of the presentinvention, there is provided a semiconductor device comprising theabove-mentioned semiconductor package and a semiconductor elementmounted on an opposite side of the semiconductor package to the sidewhere the external connection terminals are bonded, electrode terminalsof the semiconductor element being electrically connected to theconductors exposed from the openings formed in the protective film.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018]FIG. 1 is a cross-sectional view showing a constitution of asemiconductor package according to one embodiment of the presentinvention;

[0019]FIG. 2A to FIG. 2P are cross-sectional views showing amanufacturing process of the semiconductor package shown in FIG. 1; and

[0020]FIG. 3 is a cross-sectional view showing a constitution of asemiconductor package according to another embodiment of the presentinvention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021]FIG. 1 is a cross-sectional view schematically showing aconstitution of a semiconductor package according to one embodiment ofthe present invention.

[0022] In the drawing, reference numeral 10 denotes a semiconductorpackage of this embodiment, which includes a laminated core portion 10 aformed by laminating a predetermined number of print wiring boards asdescribed layer, and build-up wiring portions 10 b formed on bothsurfaces of the laminated core portion 10 a by laminating apredetermined number of layers in accordance with a build-up method. Asemiconductor element (chip) 1 is mounted on this semiconductor package10 as illustrated with broken lines via electrode terminals 2 (such assolder bumps or gold (Au) bumps) thereof.

[0023] In the semiconductor package 10, reference numerals 11 a, 11 band 11 c denote insulative base members as core members of respectiveprint wiring boards to be described later. Reference numerals 12 a, 12 band 12 c denote wiring layers severally formed on both surfaces of theinsulative base members 11 a, 11 b and 11 c by patterning. Referencenumerals 13 a, 13 b and 13 c denote resin layers severally formed by anelectrophoretic deposition process (to be described later) on surfacesof the wiring layers 12 a, 12 b and 12 c. Reference numerals 14 a, 14 band 14 c denote wiring layers severally formed on the both surfaces ofthe insulative base members 11 a, 11 b and 11 c inclusive of the resinlayers 13 a, 13 b and 13 c by patterning. Reference numeral 15 denotesprepreg layers (insulating layers) functioning as adhesive layers uponlamination of the respective print wiring boards. Reference numeral 16denotes conductors filled in through holes formed in predeterminedpositions of the laminated core portion 10 a. Reference numeral 17denotes wiring layers (inclusive of pads) formed on the insulatinglayers 15 by patterning so as to be electrically connected to theconductors 16. Reference numeral 18 denotes resin layers (insulatinglayers) formed on the wiring layers 17 and on the insulating layers 15.Reference numeral 19 denotes via holes formed on the resin layers 18 soas to reach the pads of the wiring layers 17. Reference numeral 20denotes wiring layers (inclusive of pads) formed on the resin layers 18by patterning so as to be filled inside the via holes 19. Referencenumeral 21 denotes resin layers (insulating layers) formed on the wiringlayers 20 and on the resin layers 18. Reference numeral 22 denotes viaholes formed on the resin layers 18 so as to reach the pads of thewiring layers 20. Reference numeral 23 denotes conductors filled in thevia holes 22. Reference numeral 24 denotes solder resist layers asprotective layers (insulating layers) formed so as to cover bothsurfaces of a multilayer wiring board other than portions on theconductors 23. Reference numeral 25 denotes nickel (Ni)/gold (Au) platedfilms formed on the conductors 23 exposed from openings of the solderresist layers 24. Reference numeral 26 denotes pins serving as externalconnection terminals upon mounting the package 10 onto a mother board orthe like. Moreover, reference numeral 27 denotes solder for bonding thepins 26 to the plated films 25 on the conductors 23 exposed from theopenings of the solder resist layer 24 on a lower side.

[0024] Meanwhile, upon mounting the semiconductor chip 1 on the package10, the electrode terminals 2 thereof (such as the solder bumps) arebonded to the plated films 25 on the conductors 23 exposed from theopenings of the solder resist layer 24 on an upper side.

[0025] The semiconductor package 10 of this embodiment is basicallycharacterized by the built-in capacitor portions, more specifically, byformation of the resin layers 13 a, 13 b and 13 c by the electrophoreticdeposition process (to be described later) on the wiring layers 12 a, 12b and 12 formed on the both surfaces of the insulative base members 11a, 11 b and 11 c used as the core members of the printed wiring boards,and further by use of the respective resin layers as dielectric layersof the capacitor portions.

[0026] The semiconductor package 10 of this embodiment is alsocharacterized by the multilayer wiring structure thereof, which isformed by laminating that the predetermined number of the printed wiringboards provided with the capacitor portions to form the laminated coreportion 10 a, and by laminating the predetermined number of the layers(which are two layers in the illustrated example) on the both surfacesof the laminated core portion 10 a in accordance with the build-upmethod to form the build-up wiring portions 10 b.

[0027] The respective resin layers 13 a, 13 b and 13 c constitute thedielectric layers of the respective capacitor portions. Accordingly, interms of characteristics of the capacitors, it is preferable that therespective resin layers 13 a, 13 b and 13 c are made of materials havinghigh dielectric constant. In this embodiment, the resin layers 13 a, 13b and 13 c are made of polyimide resin blended with inorganic fillerhaving high dielectric constant (wherein the dielectric constant thereofis 20 or higher, for example). Moreover, each of the pins 26electrically connected to the respective wiring layers 12 a, 12 b and 12c through the conductors 16, the respective wiring layers 17 and 20, theconductors 23 and the plated films 25, constitutes a first electrode ofeach of the capacitor portions. Meanwhile, each of the pins 26electrically connected to the respective wiring layers 14 a, 14 b and 14c formed on the respective resin layers 13 a, 13 b and 13 c through theconductors 16, the respective wiring layers 17 and 20, the conductors 23and the plated films 25, constitutes a second electrode of each of thecapacitor portions.

[0028] Ceramic powder with grain sizes within 5 μm, for example, is usedas the organic filler (dielectric material) having the dielectricconstant of 20 or higher. Preferably, ceramic powder having a perovskitestructure (such as BaTiO₃, PZT, or SrTiO₃) is used therefor. Although acommercially available product can be used as the dielectric powder ofthe above-mentioned types, it is desirable that the powder is used afterprovided with a thermal process. For example, if SrTiO₃ is used as thedielectric powder, it is desirable that SrTiO₃ is subjected to a processfor one hour or longer at a heating temperature no less than 600° C. inthe atmosphere.

[0029] Meanwhile, materials to be used for the insulative base members11 a, 11 b and 11 c include, for example, glass fabric impregnated withinsulative resin (such as epoxy resin, polyimide resin, BT resin or PPEresin), polyimide films coated with a polyimide-type thermoplasticadhesive on both surfaces thereof, or the like. Moreover, a materialmade of glass fabric impregnated with thermosetting epoxy resin or thelike and processed into a sheet at a semi-hardened B stage is used asthe prepreg layer 15. Moreover, copper (Cu) is used as the material forthe wiring layers 12 a, 12 b, 12 c, 14 a, 14 b, 14 c, 17 and 20 as wellas for the conductors 16 and 23. Furthermore, koval plated with Ni/Au,for example, is used as the material for the pins 26.

[0030] Now, description will be made regarding a method of manufacturingthe semiconductor package 10 of this embodiment with reference to FIG.2A to FIG. 2P, which sequentially illustrate the manufacturing stepsthereof.

[0031] In the first step (FIG. 2A), the insulative base member 11 aserving as the core member of the printed wiring board is prepared, andthen wiring patterns (the wiring layers 12 a) of predetermined shapesare formed on both surfaces thereof severally by photolithography.

[0032] To be more precise, a sheet member made of glass fabricimpregnated with insulative resin (such as epoxy resin, polyimide resinor BT resin) is used for example, and copper foils are adhered to bothsurfaces of this sheet member by thermal press (which is so-called a“copper-clad laminate”) upon preparation of the insulative base member11 a. Thereafter, dry films, for example, are attached to both surfacesof the copper-clad laminate as photosensitive resists bythermocompression bonding. Then, the dry films are subjected to exposureand development in accordance with predetermined shapes using masks(patterning the dry films), whereby openings are formed on the dry filmsat the portions other than the portions corresponding to thepredetermined shapes. Thereafter, the copper foils at the portionscorresponding to regions of the openings are removed by wet etchingusing an acidic solution, for example. Finally, the dry films are peeledoff. In this way, it is possible to form the wiring patterns (the wiringlayers 12 a) of the predetermined shapes. Each of the wiring layers 12 athus formed constitutes a first electrode layer of each of the capacitorportions.

[0033] In the next step (FIG. 2B), surfaces of the wiring layers 12 aare covered with polyimide resin using the electrophoretic depositionprocess, whereby the resin layers 13 a are formed thereon.

[0034] Specifically, as exemplified on the right side of the drawing, asolvent (such as ethanol) containing colloidal dispersion of polyimideresin (an inorganic filler composition) is prepared in an electrolyticcell 40. Then the structure fabricated in the precedent step (theinsulative base member 11 a provided on the both surfaces with thewiring layers 12 a) is soaked in the electrolytic cell 40, and electricfield (a power source 41) of a given magnitude is applied between theelectrolytic bath 40 and the wiring layers 12 a severally serving aselectrodes. Accordingly, the colloid is electrophoresed by this electricfield, whereby the polyimide resin covers the surfaces of the wiringlayers 12 a (formation of the resin layers 13 a). The resin layers 13 athus formed constitute the dielectric layers of the capacitor portions.

[0035] In the next step (FIG. 2C), wiring patterns (the wiring layers 14a) of predetermined shapes are formed on both surfaces of the insulativebase member 11 a inclusive of the resin layers 13 a severally byphotolithography.

[0036] To be more precise, thin-film Cu layers are firstly formed on theentire surfaces of the insulative base member 11 a and the resin layers13 a by sputtering or electroless plating of Cu. Then, conductive layersare formed on the thin-film Cu layers by electrolytic plating of Cuusing the thin-film Cu layers as feed layers. Thereafter, the wiringlayers 14 a are formed by patterning the conductive layers intopredetermined shapes.

[0037] The wiring layers 14 a can be formed by a similar process to theprocess performed in the step of FIG. 2A. Specifically, photosensitivedry films are attached to surfaces of the conductive layers (the Culayers) formed on the insulative base member 11 a and the resin layers13 a. Then, the dry films are subjected to exposure and development inaccordance with predetermined shapes using masks (patterning the dryfilms), whereby openings are formed on the dry films at the portionsother than the portions corresponding to the predetermined shapes.Thereafter, the copper layers at the portions corresponding to regionsof the openings are removed by wet etching, for example. Finally, thedry films are peeled off. In this way, it is possible to form the wiringpatterns (the wiring layers 14 a) of the predetermined shapes. Each ofthe wiring layers 14 a thus formed constitutes a second electrode layerof each of the capacitor portions.

[0038] According to the foregoing steps, a printed wiring board 30 aincluding the capacitor portions (the wiring layers 12 a and 14 a, andthe resin layers 13 a) is fabricated.

[0039] In the next step (FIG. 2D), a predetermined number layers (whichare three layers in the illustrated example) of printed wiring boards 30a, 30 b and 30 c are prepared similarly in accordance with the processperformed in the steps from FIG. 2A to FIG. 2C. Then, the respectiveprinted wiring boards 30 a, 30 b and 30 c are mutually aligned andstacked while sandwiching the prepregs 15 alternately.

[0040] In the next step (FIG. 2E), the respective printed circuit boards30 a, 30 b and 30 c, which are stacked together while sandwiching theprepregs 15 alternately, are laminated by thermal press in a vacuumambiance to form the laminated core portion 10 a.

[0041] In the next step (FIG. 2F), through holes 31 are formed inpredetermined positions on the laminated core portion 10 a formed in theprecedent step, by a drilling process with a mechanical drill or alaser, for example. A YAG laser, a CO₂ laser, an excimer laser or thelike, is used as the laser therein.

[0042] As will be described later, the through holes 31 are provided inorder to connect mutually corresponding wiring layers (mutually amongthe wiring layers 12 a, 12 b and 12 c constituting the first electrodelayers of the capacitor portions, and mutually among the wiring layers14 a, 14 b and 14 c constituting the second electrode layers of thecapacitor portions) of the respective printed boards (30 a, 30 b and 30c in FIG. 2D) electrically via the conductors 16 to be filled inside thethrough holes 31. Therefore, the positions for forming the through holes31 are selected from a region where the resin layers 13 a are formed onthe insulative base member 11 a (FIG. 2C) via the wiring layers 12 a butnot covered with the wiring layers 14 a, and from a region where thewiring layers 14 a are formed directly on the insulative base member 11a. Furthermore, in the illustrated example, the through hole 31 is alsoformed in a region where the wiring layers 12 a and 14 a are not formedon the insulative base member 11 a.

[0043] In the next step (FIG. 2G), thin-film Cu layers 32 are formed onentire surfaces of the laminated core portion 10 a inclusive of innerwalls of the through holes 31 by sputtering or electroless plating ofCu.

[0044] In the next step (FIG. 2H), the conductors 16 (which is Cu inthis case) are filled into the through holes 31. Such filling isperformed using an electrolytic plating process or a printing method.

[0045] In the case of the electrolytic plating process, for example, Cuis filled inside the through holes 31 by electrolytic plating using thethin-film Cu layers 32 formed in the precedent step as feed layers,whereby the Cu layers 16 are formed on the thin-film Cu layers 32.Meanwhile, in the case of the printing process, Cu paste is applied andfilled into the through holes 31 by screen printing.

[0046] Upon filling the inside of the through holes 31 in this step, asshown in the drawing, small dimples are formed on surfaces of the Culayers 16 at portions corresponding to the positions of the throughholes 31. In other words, the surfaces of the Cu layers 16 are leftuneven.

[0047] In the next step (FIG. 2I), uneven portions on the surfaces ofthe Cu layers 16 are polished by mechanical polishing, for example,whereby both surfaces of the laminated core portion 10 a are planarizeduntil surfaces of the prepreg layers (the insulating layers) 15 areexposed.

[0048] In the next step (FIG. 2J), wiring patterns (the wiring layers17) of predetermined shapes are formed on the both surfaces of thelaminated core portion 10 a including the through holes filled with theconductors 16.

[0049] To be more precise, thin-film Cu layers are formed on the bothsurfaces of the laminated core portion 10 a by electroless plating ofCu, and then Cu layers are formed on entire surfaces by electrolyticplating of Cu using the thin-film Cu layers as feed layers. Thereafter,the Cu layers are patterned into the predetermined shapes byphotolithography to form the wiring layers 17 (inclusive of pads). Thewiring layers 17 severally constitute primary wiring layers of thebuild-up wiring portions 10 b disposed on and under the laminated coreportion 10 a.

[0050] In the next step (FIG. 2K), thermosetting polyimide resin or thelike is applied to entire surfaces of the insulating layers 15 and thewiring layers 17, and then the resin is hardened by heating so as toform the resin layers (the insulating layers) 18.

[0051] In the next step (FIG. 2L), the via holes 19 of truncated coneshapes are formed on predetermined positions on the resin layers 18 soas to reach the pads (the wiring layers 17) thereunder using the processsimilar to the drilling process with the laser, which is performed inthe step of FIG. 2F.

[0052] In the next step (FIG. 2M), the wiring layers 20, the resinlayers (the insulating layers) 21 and the via holes 22 are sequentiallyformed as similar to the process performed in the steps from FIG. 2J toFIG. 2L, and then the inside of the via holes 22 are finally filled withthe conductors 23 to form a multilayer wiring board 10 c.

[0053] Specifically, the patterned wiring layers 20 (inclusive of pads)are formed on the resin layers 18 including the inside of the via holes19. Then, the resin layers 21 are formed on the resin layers 18 and thewiring layers 20, and the via holes 22 of truncated cone shapes areformed in the predetermined positions on the resin layers 21 so as toreach the pads (the wiring layers 20) thereunder. Finally, the inside ofthe via holes 22 are filled with the conductors 23 (which is Cu in thiscase). Such filling can be performed using an electrolytic platingprocess or a printing method.

[0054] Here, the wiring layers 20 constitute secondary wiring layers ofthe build-up wiring portions 10 b disposed on and under the laminatedcore portion 10 a. At the same time, the wiring layers 20 areelectrically connected to the primary wiring layers 17 via theconductors (Cu) filled in the via holes 19.

[0055] In the next step (FIG. 2N), the solder resist layers 24 asprotective layers are formed on both surfaces of the multilayer wiringboard 10 c, and openings 24 a are formed on the respective solder resistlayer 24 at portions corresponding to positions of the conductors 23thereunder.

[0056] To be more precise, photosensitive solder resist is applied tothe both surfaces of the multilayer wiring board 10 c by screenprinting, for example (formation of the solder resist layers 24), andthen the respective solder resist layers 24 are subjected to exposureand development using masks (not shown) severally patterned into thepredetermined shapes (patterning the solder resist layers 24), wherebythe portions of the respective solder resist layers 24 corresponding tothe positions of the conductors 23 thereunder are made open (formationof the openings 24 a). In this way, only the conductors 23 are exposedfrom the openings 24 a and the other portions are covered with thesolder resist layers 24.

[0057] In the next step (FIG. 20), electrolytic plating of Ni and Au issequentially provided on the conductors 23 exposed from the openings 24a of the solder resist layers 24 using the conductor 23 as a feedinglayer, whereby Ni/Au plated films 25 are formed.

[0058] Such formation of the Ni/Au plated films 25 enhances adhesion tothe conductors (Cu) 23 and contributes to an enhancement of conductivityupon bonding the pins 26 in the next step and conductivity upon bondingthe electrode terminals 2 of the semiconductor chip 1 in the later step.

[0059] In the last step (FIG. 2P), the pins 26 as external connectionterminals are bonded to the Ni/Au plated films 25 on the respectiveconductors 23 exposed from the openings of the lower solder resist layer24.

[0060] Specifically, an appropriate amount of paste solder 27 is put onthe Ni/Au plated film 25 on each of the conductors 23. Then, theT-shaped pin 26 having a head as large as the opening is disposedthereon in a manner that the head is located downward (located upward inthe illustrated example, because the multilayer wiring board 10 c isturned over after finishing this step). Thereafter, the solder 27 ishardened by reflow and the pin 26 is fixed accordingly.

[0061] According to the foregoing steps, the semiconductor package 10(FIG. 1) of this embodiment is fabricated.

[0062] In the above-described method of manufacturing the semiconductorpackage 10, the inside of the through holes 31 are filled with theconductors 16 (as shown in FIG. 2H) in order to exemplify containment ofthe capacitor portions, which is the characteristic of the presentinvention. However, the through holes provided in the regions other thanthe region of the capacitor portions do not have to be filled withconductors. Specifically, the insides of the through holes provided inthe regions other than the region of the capacitor portions may befilled with insulators (resin such as thermosetting polyimide resin orepoxy resin, for example).

[0063] When the semiconductor chip 1 is mounted on the semiconductorpackage 10 of this embodiment to obtain a semiconductor device, the chip1 is mounted in a manner that the electrode terminals 2 of thesemiconductor chip 1 (such as solder bumps) are connected electricallyto the plated films 25 on the respective conductors 23 exposed from theopenings on the upper solder resist layer 24 of the package 10. Suchmounting can be performed by flip-chip mounting, for example, by ACFmounting using an anisotropic conductive film (ACF).

[0064] Moreover, when the package 10 is mounted on a mounting board suchas a mother board, an appropriate amount of paste solder is put onconductors (pads) corresponding to the board, and legs of the pins 26are put thereon. Then, the solder is hardened by reflow so as toelectrically connect the both members.

[0065] As described above, according to the semiconductor package 10 andthe method of manufacturing the same according to this embodiment, thecapacitor portions are constituted in such a manner that: the dielectriclayers are composed of the resin layers 13 a, 13 b and 13 c, which areformed on the surfaces of the wiring layers 12 a, 12 b and 12 c on theinsulative base members 11 a, 11 b and 11 c using the electrophoreticdeposition process; the first electrode layers are composed of the pins26, which are electrically connected to the respective wiring layers 12a, 12 b and 12 c through the conductors 16, the wiring layers 17 and 20,the conductors 23 and the plated films 25; and the second electrodelayers composed of the pins 26, which are electrically connected to therespective wiring layers 14 a, 14 b and 14 c severally formed on theinsulative base members 11 a, 11 b and 11 c inclusive of the resinlayers 13 a, 13 b and 13 c, through the conductors 16, the wiring layers17 and 20, the conductors 23 and the plated films 25. Therefore, it ispossible to realize a suppression of occurrence of crosstalk noisesbetween a plurality of wiring, or a suppression of variation in electricpotential of a power source line.

[0066] Moreover, some of the members constituting the semiconductorpackage 10 (namely, the wiring layers 12 a, 12 b and 12 c, the wiringlayers 14 a, 14 b and 14 c, and the resin layers 13 a, 13 b and 13 c)are also used as the respective electrode layers and as the dielectriclayers of the capacitor portions. Accordingly, it is unnecessary tobuild a sheet member into the package for capacitor elements asencountered in the prior art. Such an advantage contributes to aformation of the low-profile semiconductor package 10 as well as to areduction in manufacturing costs.

[0067] In the foregoing embodiment, description has been made regardingthe case where the pins 26 are applied as the external connectionterminals for mounting the semiconductor package 10 on a mother board orthe like. However, it is needless to say that the shape of the externalconnection terminals is not limited to the pins. For example, it is alsopossible to adopt a ball shape as seen in BGA or the like. FIG. 3 showssuch an example.

[0068]FIG. 3 schematically shows a cross-sectional constitution of asemiconductor package 50, which applies solder balls 28 as the externalconnection terminals. Since other parts of the constitution are similarto the embodiment shown in FIG. 1, description thereof will be omitted.

[0069] Moreover, in the semiconductor packages 10 and 50 according tothe foregoing embodiments, description has been made regarding themultilayer wiring structure composed of the laminated core portion 10formed by laminating the printed wiring boards severally provided withthe capacitor portions, and the build-up wiring portions 10 b formed onthe both surfaces thereof using the build-up method. However, it isneedless to say that the form of the package is not limited thereto. Asit is obvious from the gist of the present invention (to form a resinlayer on a wiring layer formed on an insulative base member using anelectrophoretic deposition process, and to use the resin layer as adielectric layer of a capacitor portion), the present invention iswidely applicable regardless of whether the form of the package is basedon lamination of a plurality of printed wiring boards by thermal press,or whether the package adopts a multilayer wiring structure using abuild-up method.

What is claimed is:
 1. A method of manufacturing a semiconductor packagecontaining a capacitor portion, the method comprising the steps of:forming a first wiring layer on an insulative base member, the firstwiring layer being patterned in a predetermined shape for serving as afirst electrode layer of the capacitor portion; forming a resin layer ona surface of the first wiring layer for serving as a dielectric layer ofthe capacitor layer by an electrophoretic deposition process; andforming a second wiring layer on the insulative base member inclusive ofthe resin layer, the second wiring layer being patterned in apredetermined shape for serving as a second electrode layer of thecapacitor portion.
 2. The method according to claim 1, furthercomprising the steps of: forming a laminated core portion by preparing apredetermined number of printed wiring boards each of which is astructure made by forming the first wiring layer, the resin layer andthe second wiring layer sequentially on the insulative base member, andby laminating the respective printed wiring boards by thermal press in avacuum ambiance while interposing prepregs severally between the printedwiring boards; forming through holes on the laminated core portionseverally in a region where the resin layer is formed via the firstwiring layer on the insulative base member but uncovered with the secondwiring layer, and in a region where the second wiring layer is formeddirectly on the insulative base member; filling insides of the throughholes with conductors; forming third wiring layers patterned intopredetermined shapes on both surfaces of the laminated core portioninclusive of the through holes filled with the conductors; forminginsulating layers on both surfaces of the laminated core portioninclusive of the third wiring layers; forming via holes in predeterminedpositions of the insulating layer so as to reach respective pads of thethird wiring layer; forming a multilayer wiring board by sequentiallyrepeating formation of a patterned wiring layer, an insulating layer andvia holes so as to constitute a required number of layers, and finallyby filling insides of the via holes with conductors; forming protectivefilms on both surfaces of the multilayer wiring board and then formingopenings in the respective protective films at portions corresponding topositions of the conductors inside the via holes; and bonding externalconnection terminals to the conductors exposed from the openings formedin one of the protective films.
 3. The method according to claim 2,between the step of forming the openings in the protective films and thestep of bonding the external connection terminals, further comprisingthe step of forming plated films on the conductors exposed from theopenings of the respective protective films.
 4. The method according toclaim 1, wherein the step of forming the resin layer by theelectrophoretic deposition process includes the steps of: preparing asolvent containing colloidal dispersion of organic resin in anelectrolytic cell; soaking the insulative base member provided with thefirst wiring layer into the electrolytic cell; and applying electricfield between the first wiring layer and the electrolytic cell tothereby utilize electrophoresis of colloid by the electric field.
 5. Themethod according to claim 4, wherein the organic resin is blended withinorganic filler made of a highly dielectric material.
 6. The methodaccording to claim 5, wherein polyimide resin is used as the organicresin.
 7. The method according to claim 5, wherein ceramic powder havinga perovskite structure is used as the inorganic filler.
 8. Asemiconductor package manufactured by the method of manufacturing asemiconductor package according to any one of claims 2 and
 3. 9. Asemiconductor device comprising: the semiconductor package according toclaim 8; and a semiconductor element mounted on an opposite side of thesemiconductor package to the side where the external connectionterminals are bonded, electrode terminals of the semiconductor elementbeing electrically connected to the conductors exposed from the openingsformed in the protective film.